This invention relates to semiconductor integrated circuit devices, and more particularly to fuse circuits of the type used in VLSI CMOS semiconductor memory devices or the like.
In self-repairing semiconductor memory devices, fuses are used to store the addresses of faulty locations, so redundant cells can be substituted. Or, the fuse may be used to generate an enabling signal. These fuses are usually polysilicon conductor strips that are selectively blown by an indexed laser beam. The enabling signal or address bit is required to be at one logic state when disabled and the opposite logic state when programmed or enabled, so there must be a circuit path from one power supply rail to the other. One technique used in prior devices to reduce power dissipation in these enabling fuses is to connect the fuse element in series with a long-channel, narrow-width MOS transistor so the static current is kept to a minimum. Another technique is to clock the gate of the MOS transistor so that power is reduced in proportion to the duty cycle of the clock. Both of these techniques consume in the order of microamps to tens of microamps of current for practical transistor dimensions. Since several of these fuse circuits are generally used in a typical memory device, the power dissipation caused by the fuse circuits becomes unacceptable, especially for situations where very low standby power is needed, usually where CMOS circuits are used.
It is therefore the principal object of this invention to provide improved fuse circuits exhibiting a low current drain for use in semiconductor integrated circuits such as memory or microcomputer devices, particularly CMOS devices with low standby power dissipation and minimum complexity.